Solid-state imaging apparatus having decoders for resetting switches

ABSTRACT

A solid-state imaging apparatus includes: a pixel region including a plurality of pixels, each including a photoelectric conversion element, arranged in matrix, and a reset switch for discharging electric charge of the photoelectric conversion element; and a first scanning circuit for supplying a reset control signal for controlling an operation of the reset switch, the pixel region and the first scanning circuit being formed on a semiconductor substrate, in which the pixel region includes a first pixel region and a second pixel region, and the first scanning circuit includes a first decoder for controlling the operation of the reset switch arranged in the first pixel region, and a second decoder for controlling the operation of the reset switch arranged in the second pixel region.

CROSS REFERENCE TO RELATED APPLICATION

This application is a division of U.S. application Ser. No. 12/267,834filed on Nov. 10, 2008 now U.S. Pat. No. 8,159,577, the entiredisclosure of which is hereby incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a solid-state imaging apparatus.

2. Description of the Related Art

Conventionally, amplification type solid-state imaging apparatuses areknown in technical fields, in which photoelectric conversion elementsand amplifying units are included in pixels, while the amplifying unitsamplify signals produced based upon electric charges of thephotoelectric conversion elements. Among the above-mentionedamplification type solid-state imaging apparatuses, general structuresthereof are constructed by providing transfer switches and resetswitches in input portions of the amplifying units, while the transferswitches transfer electric charges of the photoelectric conversionelements, and the reset switches reset the input portions of theamplifying units.

As a solid-state imaging apparatus having an electronic shutterfunction, Japanese Patent Application Laid-Open No. H08-336076 hasdisclosed such a structure which includes a vertical scanning circuitfor controlling transfer switches, and another vertical scanning circuitfor controlling reset switches. In the above-mentioned solid-stateimaging apparatus having the electronic shutter function of JapanesePatent Application Laid-Open No. H08-336076, the scanning operation ofthe reset scanning-type vertical scanning circuit is performed at acertain time, whereby the respective pixels are reset. Thereafter, sincethe scanning operation of the transfer scanning type vertical scanningcircuit is performed at another time, an accumulation time period,namely, a shutter time period can be determined (namely, electronicshutter).

Also, Japanese Patent Application Laid-Open No. 2005-094142 hasdisclosed an arrangement in which reset scanning circuits capable ofperforming resetting operations two times within 1 frame have beenarranged in a dual system in order to solve such a problem that when ascaling factor is switched during electronic zooming in a structure forperforming an electronic shutter, exposure time periods are differentfrom each other every row.

However, in the dual system arrangement of Japanese Patent ApplicationLaid-Open No. 2005-094142, there is such a problem that the circuitscale of the reset vertical scanning circuit is increased. The resetscanning circuits arranged in the dual system are alternately operatedevery time a timing signal is output from a timing control unit. As aconsequence, it is required to construct that both the reset scanningcircuits arranged in the dual system can access with respect to all rowsof pixel regions. Both the reset scanning circuits capable of accessingall of those rows are arranged, and hence the circuit scale isincreased, and the chip area is increased. Otherwise, a degree offreedom as to an element layout is decreased. In some cases, theabove-mentioned accessible arrangement of the reset scanning circuit mayconduct that an area of pixel regions is decreased.

The present invention has been made to solve the above-mentionedproblems, and has an object to provide such a solid-state imagingapparatus capable of performing reset scanning a plurality of timeswithin 1 frame without increasing a circuit scale of the solid-stateimaging apparatus.

SUMMARY OF THE INVENTION

In order to achieve the above-mentioned object, a solid-state imagingapparatus according to one aspect of the present invention includes: apixel region including a plurality of pixels, each including aphotoelectric conversion element, arranged in matrix, and a reset switchfor discharging electric charge of the photoelectric conversion element;and a first scanning circuit for supplying a reset control signal forcontrolling an operation of the reset switch, the pixel region and thefirst scanning circuit being formed on a semiconductor substrate, inwhich the pixel region includes a first pixel region and a second pixelregion, and the first scanning circuit includes a first decoder forcontrolling the operation of the reset switch arranged in the firstpixel region, and a second decoder for controlling the operation of thereset switch arranged in the second pixel region.

Other features and advantages of the present invention will be apparentfrom the following description taken in conjunction with theaccompanying drawings, in which like reference characters designate thesame or similar parts throughout the figures thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates an entire structure of a solid-stateimaging apparatus according to a first embodiment of the presentinvention.

FIG. 2 is an equivalent circuit diagram of a unit pixel of thesolid-state imaging apparatus of the first embodiment.

FIGS. 3A and 3B represent pulse waveforms when resetting operation andreading out operation are performed in the first embodiment.

FIG. 4A is a structural diagram of a logic circuit provided in the firstembodiment, and FIG. 4B illustrates a pulse diagram of the logic circuitillustrated in FIG. 4A.

(a), (b), (c) and (d) of FIG. 5 are timing charts for indicatingtransitions as to both timing and count values of electronic shutteroperation of the solid-state imaging apparatus according to the firstembodiment.

(a), (b), (c) and (d) of FIG. 6 are timing charts for indicatingtransitions as to both timing and count values of electronic shutteroperation of a solid-state imaging apparatus according to a secondembodiment of the present invention.

FIG. 7 is a diagram for describing a relationship change amounts betweenan accumulation time period of an n frame, and an accumulation timeperiod of a frame subsequent to the n frame in the solid-state imagingapparatus of the second embodiment.

FIG. 8 schematically illustrates an entire structure of a solid-stateimaging apparatus according to a third embodiment of the presentinvention.

(a), (b), (c), (d) and (e) of FIG. 9 are timing charts for indicatingtransitions as to both timing and count values of electronic shutteroperation of the solid-state imaging apparatus according to the thirdembodiment of the present invention.

FIG. 10 is a diagram for describing a change in accumulation time periodin the third embodiment.

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention.

DESCRIPTION OF THE EMBODIMENTS First Embodiment

FIG. 1 is a conceptional diagram for illustrating a structure of asolid-state imaging apparatus according to a first embodiment of thepresent invention. Reference numeral 1-1 indicates a pixel region inwhich a plurality of photoelectric conversion elements and a pluralityof switches (reset switches) for discharging electric charges of thephotoelectric conversion elements are arranged in matrix. Theabove-mentioned pixel region 1-1 includes a first pixel region 1-1 a anda second pixel region 1-1 b.

In order to perform electronic shutter operation, the pixel region 1-1is required to include at least the reset switches. Since the electriccharges of the photoelectric conversion elements are discharged by thereset switches at arbitrary switching timing, a start of an accumulationtime period can be defined. Alternatively, in addition to the resetswitches, the pixel region 1-1 may include an amplifying unit foramplifying signals produced based upon the electric charges of thephotoelectric conversion elements, and transfer switches fortransferring the electric charges of the photoelectric conversionelements to an input portion of the amplifying unit. The transferswitches are provided in correspondence with the respectivephotoelectric conversion elements, whereas the amplifying unit may beprovided with respect to each of those photoelectric conversionelements, or may be provided every plurality of sets of thephotoelectric conversion elements.

A read-out circuit 1-2 reads out a signal derived from the pixel region1-1. For instance, the read-out circuit 1-2 includes amplifiers (columnamplifiers), a CDS circuit, and the like. For instance, the columnamplifiers are provided every pixel column.

A horizontal scanning circuit 1-3 sequentially reads signals to which apredetermined processing has been carried out by the read-out circuit1-3. An output amplifier 1-9 amplifies the signals sequentially read outby the horizontal scanning circuit 1-3, and then, outputs the amplifiedsignals.

Decoders 1-6 a and 1-6 b generate electric charge reset pulses which areutilized in order to discharge electric charges of the photoelectricconversion elements. A vertical scanning circuit (first scanningcircuit) includes the first decoder 1-6 a and the second decoder 1-6 b.The vertical scanning circuit supplies reset control signals which areemployed so as to scan the reset switches. The first decoder 1-6 a scanspixel rows arrayed in the first pixel region 1-1 a, whereas the seconddecoder 1-6 b scans pixel rows arrayed in the second pixel region 1-1 b.In this case, the first and second pixel regions 1-1 a and 1-1 b neednot be arranged in such a manner that pixel regions are clearlyseparated from each other, but may be alternatively arranged based uponsets of pixel rows which are scanned by the first decoder 1-6 a and thesecond decoder 1-6 b respectively.

Reference numerals 1-7 a, 1-7 b, and 1-7 c indicate counters. Thosecounters 1-7 a, 1-7 b, and 1-7 c are provided in correspondence with thefirst decoder 1-6 a, the second decoder 1-6 b, and a read-out decoder1-5 (will be discussed later), respectively.

Reference numeral 1-5 denotes an electric charge read-out decoder withrespect to the photoelectric conversion elements. Another verticalscanning circuit (second scanning circuit) includes the read-out decoder1-5 for supplying transfer control signals for controlling operations ofthe transfer switches. The decoder 1-5 is controlled by the counter 1-7c.

Reference numeral 1-4 denotes a logic circuit. Output signals of thedecoders 1-5, 1-6 a, 1-6 b, and also a control pulse generated from atiming generator (TG) 1-8 are input to the logic circuit 1-4 in order toproduce the above-mentioned reset control signal and transfer controlsignal. The logic circuit 1-4 constitutes a portion of theabove-mentioned first scanning circuit and second scanning circuit.

Reference numeral 1-8 denotes a timing generating circuit. The counters1-7 a to 1-7 c are controlled, whereby the timing generating circuit 1-8functions as a control circuit for controlling timing based upon countvalues to be supplied to the decoders 1-6 a and 1-6 b. This controlcircuit is arranged in such a manner that at least only a structurethereof for generating a timing pulse is arranged on the samesemiconductor substrate as the pixel region 1-1. Then, functions of thiscontrol circuit, which define a reading out region within the pixelregion 1-1 and an accumulation time period (will be discussed later) maybe alternatively provided as a separate body.

The above-mentioned structural elements are formed on the semiconductorsubstrate in a monolithic manner. As previously described, a portion ofthe timing generating circuit (TG) 1-8 may be alternatively constructedas a separate body.

FIG. 2 indicates an example as to an equivalent circuit of a unit pixelarranged in the pixel region 1-1. In this example, the unit pixelincludes a photoelectric conversion element and a reset switch, and inaddition thereto, includes the above-mentioned amplifying unit andtransfer switch.

In FIG. 2, a photoelectric conversion element 2-1 performs aphotoelectric conversion and, for example, a photodiode (PD) may beemployed. Reference numeral 2-4 represents a portion of an amplifyingunit for amplifying a signal produced based upon electric chargesgenerated by the photoelectric conversion element 2-1. Morespecifically, the amplifying unit 2-4 corresponds to a source followercircuit including a MOS transistor, while the MOS transistor converts anelectric charge transferred to a gate of this MOS transistor into avoltage. As a consequence, the gate of the MOS transistor may alsofunction as an input portion of the amplifying unit. Further, the gateof the amplifying-purpose MOS transistor is electrically connected to afloating diffusion region (FD) arranged on the semiconductor substrate.

A transfer switch 2-2 reads out electric charges of the photodiode (PD)2-1 to the input portion of the amplifying unit. As the transfer switch2-2, a MOS transistor may be employed, while a pulse pTX is applied to agate of this MOS transistor, and the gate thereof becomes a controlelectrode.

A reset switch 2-3 discharges electric charges of the photoelectricconversion element 2-1. As the reset switch 2-3, a MOS transistor can beemployed, while a pulse pRES is applied to a gate of the MOS transistor,and the gate thereof becomes a control electrode. In response to thepulse pRES, an operation of the reset switch 2-3 is controlled.

FIG. 3A and FIG. 3B represent waveforms of pulses which are supplied tothe transfer switch and the reset switch in a reading out operation anda resetting operation in the first embodiment. Both the transfer switchand the reset switch become active in response to a High status pulse,whereby the switches are enabled.

FIG. 3A is a pulse diagram of such a reading out operation that anarbitrary pixel row is selected by the read-out decoder 1-5 so as toperform the reading out operation. Firstly, the pulse pTX is under Lowstatus, and the pulse pRES becomes a High status. As a result, apotential at the input portion of the amplifying unit is reset. Then, asignal having this status is read out from the pixel region 1-1, and theread signal is held as a noise signal of the pixel, if necessary. Next,after the status of the pulse pRES is brought into a Low status, thestatus of the pulse pTX is brought into a High status and the electriccharge of the photoelectric conversion element is transferred to theinput portion of the amplifying unit. Then, the signal having thisstatus is read out from the pixel region 1-1, and if required, adifference processing between the read signal and the above-mentionednoise signal is carried out, thereby obtaining a signal of 1 pixel. Inother words, in this example, the reading out operation implies such areading out operation that the electric charges of the photoelectricconversion element are transferred to the input portion of theamplifying unit, and then, the amplified signal is read out from thepixel region 1-1.

FIG. 3B indicates waveforms of pulses when a resetting operation iscarried out. Firstly, the signal level of the pulse pRES becomes High,and under this condition, the signal level of the pulse pTX becomesHigh. When the above-mentioned operation is carried out, the electriccharges of the photoelectric conversion element are discharged via thereset switch. The above-mentioned operation corresponds to the resettingoperation. With respect to an accumulation time period conducted in thefirst embodiment, an accumulation starting time is determined by theresetting operation, and an accumulation end time is determined by thereading out operation.

FIG. 4A illustrates one example as to a concrete structure of the logiccircuit 1-4, and FIG. 4B represents waveforms of pulses which aresupplied to the logic circuit 1-4. The structural example illustrated inFIG. 4A is a portion corresponding to one pixel row of a pixel arrayarranged in matrix.

In FIG. 4A, the logic circuit includes an input portion 3-1 to which theoutput of the reset decoder 1-6 is supplied, and another input portion3-2 to which the output of the read-out decoder 1-5 is supplied. Theabove-mentioned logic circuit further includes a first AND circuit 301and a third AND circuit 303, in which the output of the reset decoder1-6 is supplied to one input portion thereof; and still further includesa second AND circuit 302 and a fourth AND circuit 304, in which theoutput of the read-out decoder 1-5 is supplied to one input portionthereof. A pulse pTXR0 is supplied to the other input portion of thefirst AND circuit 301, whereas another pulse pTX0 is supplied to theother input portion of the second AND circuit 302. Also, a pulse pRESR0is supplied to the other input portion of the third AND circuit 303,whereas another pulse pRES0 is supplied to the other input portion ofthe fourth AND circuit 304.

FIG. 4B represents an example of a pulse waveform diagram for indicatingthe pulses pTX0, pTXR0, pRES0, and pRESR0. The above-mentioned pulsespTX0 and pTXR0 correspond to read-out pulses, namely the pulses used togenerate the pulse pTX. Then, the above-mentioned pulses pRES0 andpRESR0 correspond to reset pulses, namely the pulses used to generatethe pulse pRES. In such a case where the signal level of the output fromthe reset decoder 1-6 is High, and the signal level of the output fromthe read-out decoder 1-5 is Low, the above-mentioned resetting operationis carried out with respect to the above-mentioned pixel row. In such acase where the signal level of the output from the reset decoder 1-6 isLow, and the signal level of the output from the read-out decoder 1-5 isHigh, the above-mentioned reading out operation is carried out withrespect to the above-mentioned pixel row.

The output pulse pTX from the logic circuit 1-4 is supplied to a gate ofthe transfer switch 2-2, and the output pulse pRES is supplied to a gateof the reset switch 2-3. As a result, both the transfer pulse pTX andthe reset pulse pRES can be supplied only to such a row which isselected by the reset decoders 1-6 a, 1-6 b, and the read-out decoder1-5.

The pulse pTX0 is supplied as the transfer pulse pTX which is suppliedto the pixel row selected by the read-out decoder 1-5, and the pulsepRES0 is supplied as the reset pulse pRES to be supplied to the selectedpixel row. The pulse pTXR0 is supplied as the transfer pulse pTX whichis supplied to the pixel row selected by the reset decoders 1-6 a and1-6 b, and the pulse pRESR0 is supplied as the reset pulse pRES to besupplied to the selected pixel row.

(a) to (d) of FIG. 5 illustrate transitions as to resetting timing,reading timing, and count values of the counter 1-7 in such a case whereall of the pixel rows are read out. (a) of FIG. 5 represents a verticalsynchronizing signal (V synchronizing signal), and timing when thedecoder accesses the respective pixel rows in such a case where theaccumulation time period is switched from Ts1 to Ts2 longer than Ts1 incontinuous image frames, since the shutter time is switched.

(b) of FIG. 5 illustrates a transition of count values of the counter1-7 a which corresponds to the decoder 1-6 a in the above-mentionedtiming. (c) of FIG. 5 indicates a transition of count values of thecounter 1-7 b which corresponds to the decoder 1-6 b. (d) of FIG. 5illustrates a transition of count values of the counter 1-7 c whichcorresponds to the decoder 1-5.

In (a) to (d) of FIG. 5, at a time t12, a reading out operation for apredetermined image frame (first frame) is started, and at a time t17, areading out operation for a next image frame (second frame) is started.An accumulation time period of the first frame is Ts1, and anaccumulation time period of the second frame is Ts2. Since the readingout operation of the first frame is started at the time t12, a resettingoperation is started from a time t11 which precedes the time period Ts1from the time t12. In the second frame, a resetting operation is startedat a time t14 which precedes the time period Ts2 from the reading outoperation time t17.

Since the accumulation time period Ts2 is longer than the accumulationtime period Ts1, two pixel rows different from each other are requiredto be reset at the same time during a time duration defined from a timet15 up to a time t16. As previously described, the reset decoders arearranged in such a manner that the decoder 1-6 a and the decoder 1-6 bcan simultaneously scan both the pixel row of the first pixel region 1-1a, and the pixel row of the second pixel region 1-1 b which is differentfrom the first pixel region 1-1 a. In other words, the decoders 1-6 aand 1-6 b are constructed in such a manner that the decoders 1-6 a and1-6 b perform the resetting operations with respect to the pixel rowswhich are arranged in the respective pixel regions different from eachother. As a consequence, the resetting operations for two pixel rows canbe carried out at the same time by those decoders 1-6 a and 1-6 b. It isarranged that both the decoders 1-6 a and 1-6 b cannot perform theresetting operations with respect to the same region within the pixelregion. If such an arrangement is employed, then the circuit scales ofthose decoders are increased, and the occupation areas of those decoderson the semiconductor substrate are increased. According to the firstembodiment, occupation areas of the decoders 1-6 a and 1-6 b can be madesubstantially half, as compared with those of such an arrangement thatboth the decoders can perform the resetting operations with respect tothe same region.

Moreover, according to the arrangement of the first embodiment, such atime (time t16 in first embodiment) when the resetting operations of thesecond frames are finished until a half of the entire pixel row may bealternatively prolonged up to the time t15 illustrated in (d) of FIG. 5.

A specific description is made of operations of the counters 1-7 a and1-7 b, and of the decoders 1-6 a and 1-6 b employed in the firstembodiment.

If the counter 1-7 a starts a count-up operation at the time t11 and thecount-up operation reaches the time t13 at which the resetting operationfor the first frame by the decoder 1-6 a reaches the ½ region of theentire pixel region, the counter 1-7 a outputs a maximum count value.Subsequently, the counter 1-7 a maintains the maximum count value untilthe time t14 at which the resetting operation for the second frame bythe decoder 1-6 a is started. When the count-up operation of the counter1-7 a reaches the time t14, this counter 1-7 a again starts a count-upoperating from zero.

Also, the counter 1-7 b starts a count-up operation at the time t13 atwhich the resetting operation for the first frame by the decoder 1-6 breaches the ½ region of the entire pixel region, and then the counter1-7 b outputs a maximum count value at the time t15 at which theresetting operation for the first frame reaches a last row. Thereafter,the counter 1-7 b maintains the maximum count value until the time t16at which the resetting operation for the second frame by the decoder 1-6b reaches the ½ region of the entire pixel region. From the time t16,the counter 1-7 b starts a count-up operation in conjunction with theresetting operation of the second frame.

The first embodiment has exemplified such a case where a frame rate Tfis equal to a time required for executing one of reading out operationsand resetting operations as to all of the pixel rows, namely, is equalto (total number of the entire pixel rows)×Th. In this formula, symbolTh indicates a time required for executing the operation for 1 pixelrow, namely, a time of 1 horizontal time period. In this case, the timeperiod Ts2 may be set longer than the time period Ts1 by Tf/2 atmaximum.

Also, when a time required for performing one of the reading outoperations and the resetting operations as to all of the pixel rows isshorter than the frame rate Tf, namely when (total row number)×Thbecomes shorter than the frame rate Tf, the time period Ts2 may bealternatively set to be longer than the time period Ts1 by Tf/2+(Tf−(allrows)×Th) at maximum. Further, in the first embodiment, the pixel regionhas been divided by ½, and the reset decoders have been divided withrespect to the respective divided pixel regions. Alternatively, adividing number, and also, a number of such pixel rows which areallocated to sub-divided decoders may be arbitrarily set.

Second Embodiment

In a second embodiment of the present invention, a description is madeof an example in which both a row where a reading out operation isstarted and an accumulation time period for electric charges in aphotoelectric conversion element are switched in two frames. Electroniczooming can be carried out by changing the row where the reading outoperation is started.

(a) to (d) of FIG. 6 illustrate timing diagrams of the secondembodiment, which are described referring to those of (a) to (d) of FIG.5. In the second embodiment, an entire circuit and a structure of a unitpixel similar to those of the first embodiment can be employed.

(a) of FIG. 6 illustrates a vertical synchronizing signal (Vsynchronizing signal), and timing when decoders access respective pixelrows in a case where shutter time is switched, whereby an accumulationtime period is switched from Ts1 to Ts2 longer than Ts1 in continuousimage frames. In addition, positions of pixel rows in which scanningoperations are started are different from each other in both imageframes.

(b) of FIG. 6 illustrates a transition of count values of the counter1-7 a which corresponds to the decoder 1-6 a at the above-mentionedtiming. (c) of FIG. 6 illustrates a transition of count values of thecounter 1-7 b which corresponds to the decoder 1-6 b. (d) of FIG. 6illustrates a transition of count values of the counter 1-7 c whichcorresponds to the decoder 1-5.

RESET 1 represents a resetting operation of a first frame, READ 1represents a reading out operation of the first frame, RESET 2represents a resetting operation of a second frame, and READ 2represents a reading out operation of the second frame.

In the first frame, it is assumed that the reading out operation isstarted from a V_shift1st row, and an accumulation time period is Ts1.In the second frame, it is assumed that the reading out operation isstarted from a V_shift2nd row, and an accumulation time period is Ts2which is longer than Ts1. It is assumed that a time period required forscanning one pixel row, namely, a time period of one horizontal timeperiod is Th.

At a time t22, the V synchronizing signal is supplied to the timinggenerating circuit TG1-8, and a scanning operation by the decoder 1-5 isstarted. A scanning start position of the decoder 1-5 is started fromthe same pixel row as a scanning start position of the reset decoder 1-6which has already been started from one preceding frame with respect tothe first frame. This scanning start position may be arbitrarilydetermined, and can be determined by setting an arbitrary value V_shiftto an initial value of a counter in this case. The decoder 1-6 aperforms a resetting operation for a pixel row of a first pixel region,and the decoder 1-6 b performs a resetting operation for another pixelrow of a second pixel region which is different from the first pixelregion. In this case, the first pixel region and the second pixel regiondo not have regions which are overlapped with each other, and form theentire pixel region.

In a resetting operation of the first frame, a scanning operation isstarted at a time t21 which precedes the time t22 by the time periodTs1. In this resetting operation, the scanning operation is started fromthe V_shift1st row. When the counter 1-7 a performs a counting operationuntil a time t23, the counter 1-7 b starts a counting operation, whichcorresponds to the decoder 1-6 b for scanning a pixel row of the secondpixel region in conjunction with the counting operation of the counter1-7 a. After the counter 1-7 b starts the counting operation, thecounter 1-7 b continues the counting operation until a last row of thepixel region is selected. After selecting operations for all pixel rowsis finished, the counter 1-7 b continuously outputs a value which islarger than the maximum number of the decoder 1-6 b until a startingsignal in conjunction with the counter 1-7 a is supplied. At the timet23, the decoder 1-6 a finishes the resetting operations for (all pixelrows/2)−V_shift1 rows. In other words, among the resetting operations ofthe first frame, the scanning operation of the pixel row where theresetting operation of the first pixel region should be carried out isfinished. Then, the counter 1-7 a resets the count value in order toperform resetting operations from the first row which has not beenselected until the time t23 up to a (V_shift1)−1 row, and then, performsa counting operation up to the (V_shift1)−1 row. After the counter 1-7 aperforms the counting operations until the (V_shift1)−1 row, similar tothe counter 1-7 b, the counter 1-7 a continuously outputs a value whichis larger than a maximum number of the decoder 1-6 a until a next countstarting signal is supplied. In other words, when a reading out regionand a non-reading out region are set in the manner similar to anelectronic zooming operation or the like, a counter corresponding to afirst decoder is set to an initial value corresponding to a head pixelrow of the reading out region. Then, after a resetting operation for thereading out region is finished, a resetting operation for thenon-reading out region located within the first pixel region is carriedout.

Through an operation described above, all of the pixel rows can be resetat least one time within one frame. In this case, at an end position ofthe reading out operation, if a count value of the counter 1-7 c reachesV_shift1+reading row number, the counter 1-7 c continuously outputs avalue larger than the maximum number of the decoder 1-5 until a next Vsynchronizing signal is supplied in a similar manner to other counters.In the second embodiment, because the V synchronizing signal is suppliedjust after the reading out operation of the first frame is finished, thecounting operation is entered to a reading out operation of a secondframe without outputting a value larger than the maximum number. V_shiftand a reading row number may be set to arbitrary values, and hence thereading position can be controlled in the unit of a single pixel.

In the second embodiment, imaging conditions such as an accumulationtime period, a reading start row, and a reading end row are set wheninstruction signals issued from a microcomputer (not illustrated) aresupplied to the timing generating circuit TG1-8. In this case, asequential operation when the microcomputer determines the imagingconditions will be describe as follows:

Condition 1: A time t24 precedes a time t25:t24<t25  (1)t24=t22+(Tf−Ts2)  (2)t25=t22+(all pixel rows/2)×Th−Ts1  (3)Condition 2: A time t26 precedes a time t27:t26<t27  (4)t26=t25+{(all pixel rows/2)−V_shift2}×Th  (5)t27=t22+(all pixel rows×V_shift1)×Th−Ts1  (6)Condition 3:V_shift×Th<Th−Ts2  (7)Ts2<Tf−V_shift×Th  (8)

The condition 1 implies a condition in which two pixel rows of a pixelregion scanned by the decoder 1-6 a at the same time are prevented frombeing simultaneously selected. In other words, the condition 1 prohibitsthat the decoder 1-6 a performs the resetting operations with respect tothe different pixel rows at the same time in the first pixel region.

The condition 2 implies a condition in which the condition 1 is appliedto the decoder 1-6 b. In other words, the condition 2 prohibits that thedecoder 1-6 b performs the resetting operations with respect to thedifferent pixel rows at the same time in the second pixel region.

The condition 3 implies a condition in which the timing of the resettingoperation for the second frame does not precede the reading outoperation of the first frame in a temporal manner in FIG. 6A to FIG. 6D.

If the condition 1 is modified, the following formula may beestablished:Ts2−Ts1<Tf−(all pixel rows/2)×Th  (9)The condition 2 may be modified as follows:Ts2−Ts1<{ΔV_shift−(all pixel rows/2)}×Th+Tf  (10)ΔV_shift is defined as:ΔV_shift=V_shift2−V_shift1  (11)Assuming that a reading start position in a certain frame is V_shift2,ΔV_shift is equal to a difference between V_shift2 and V_shift1 whichcorresponds to a reading start position immediately preceding framethereof.

(a) to (d) of FIG. 6 illustrate a relationship between Ts1 and Ts2−Ts1in a case where a maximum Δ V_shift and a minimum ΔV_shift are set tofixed values. According to the second embodiment, in a case where themaximum ΔV_shift and the minimum ΔV_shift are set to the fixed values, amaximum ΔTs2 (change amount of Ts2) which can be changed until Ts1becomes (all pixel rows/2)×Th may be given as a constant value definedas:Tf+{ΔV_shift−1−(all pixel rows/2)}×Th.

This is determined by the condition 2. Then, the maximum changeable ΔTs2is decreased at an inclination of −1.

In a case where an imaging operation is carried out at a constant framerate, if Ts1 becomes Tf+(ΔV_shift−1)×Th, an accumulation time periodcannot be prolonged. In order to prolong the accumulation time periodfurther, the frame rate is lowered and Tf is prolonged.

In the second embodiment, the instruction signals are supplied from themicrocomputer to the timing generating circuit TG within a rangesatisfying the above-mentioned three conditions, and hence both theaccumulation time period and the reading start position can bearbitrarily set for every frame. As a result, the sensor can be drivenin response to a change in brightness when a moving picture isphotographed. Moreover, the sensor can be driven with respect toelectronic vibration isolation. Further, because the scanning circuitsare formed not by shift registers, but by the decoders, the scanningcircuits can be easily driven in various modes such as an addition mode,an interlace mode, a progressive mode, and a thinning-out mode.

From another viewpoint, in the second embodiment, all of the pixels canbe surely selected one time for every frame by the reset decoders, andhence the charges of the photoelectric conversion elements other thanthe reading out region can also be reset. As a result, the bloomingeffect from the photoelectric conversion elements other than the readingout region can be suppressed, and hence images having high imagequalities can be photographed.

In the second embodiment, the reset decoders are divided so that thepixel region is divided into two (namely, first pixel region and secondpixel region). Alternatively, a total number of sub-divisions, and atotal number of pixel rows which are allocated to one decoder may bearbitrarily set. As described in the first embodiment, it is notnecessarily required that the pixel region is clearly divided.

Further, in a case where a dividing number of the decoders and scanningpatterns are changed, driving conditions given under the dividing numberand the vertical scanning pattern may be newly set by theabove-mentioned microcomputer.

Third Embodiment

In a third embodiment of the present invention, a description is made ofa case where a pixel region is divided into two pixel regions, decodersare provided in correspondence with those two divided pixel regions, andfurther, another decoder (third decoder) is provided so as to scan anoptical black (OB) row. As in the case of the second embodiment, a pixelrow in which a reading out operation is started and an accumulation timeperiod are switched between two continuous frames. The structures andthe operations described in the first and second embodiments except foran operation related to the optical black region may be applied tostructures and operations of the third embodiment.

FIG. 8 illustrates an entire structure of the solid-state imagingapparatus according to the third embodiment. Reference numerals 7-1 aand 7-1 b denote effective pixel regions in which a plurality of unitpixels illustrated in FIG. 2 are arranged in array. Reference numeral7-1 c denotes an OB region. A read-out circuit 7-2 reads out signalsfrom the pixel regions. A horizontal scanning circuit 7-3 sequentiallyreads out signals which have been subjected to a predeterminedprocessing by the read-out circuit 7-2. An output amplifier 7-9amplifies signals which have been sequentially read out. Referencenumeral 7-6 a denotes a reset decoder (namely, third decoder) providedfor the OB region. Reference numerals 7-6 b and 7-6 c denote resetdecoders provided for the effective pixel regions 7-1 a and 7-1 b. Thedecoders 7-6 a, 7-6 b, and 7-6 c have counters 7-7 a, 7-7 b, and 7-7 c,respectively. Reference numeral 7-5 denotes a reading decoder which iscontrolled by the counter 7-7 d. In the third embodiment, the counters7-6 b and 7-6 c perform scanning operations for (effective pixel rows/2)rows, respectively. It should be noted that this pixel row number may bearbitrarily set.

Reference numeral 7-4 denotes a logic circuit to which the decoders 7-6a to 7-6 c outputs, and a control pulse from a timing generator (TG) 7-8is input. Since a specific circuit for 1 row of the logic circuit 7-4,and the control pulse may be realized by employing those similar to thefirst and second embodiments, a description thereof will be omitted.

(a) to (e) of FIG. 9 illustrate timing charts in the third embodiment,which are described referring to (a) to (d) of FIG. 5, and (a) to (d) ofFIG. 6. (a) of FIG. 9 illustrates a vertical synchronizing signal (Vsynchronizing signal) and timing when the decoders 7-6 a to 7-6 c, and7-5 access respective pixel rows in a case where shutter time isswitched, and an accumulation time period is switched from a time periodTs1 to another time period Ts2 which is longer than the time period Ts1in continuous image frames. In addition, positions of pixel rows wherescanning operations are started are different from each other in boththe image frames.

(b) of FIG. 9 illustrates a transition of count values of the counter7-7 a which corresponds to the decoder 7-6 a at the above-mentionedtiming. (c) of FIG. 9 illustrates a transition of count values of thecounter 7-7 b which corresponds to the decoder 7-6 b. (d) of FIG. 9illustrates a transition of count values of the counter 7-7 c whichcorresponds to the decoder 7-6 c. (e) of FIG. 9 illustrates a transitionof count values of the counter 7-7 d which corresponds to the decoder7-5.

RESET 1 represents a resetting operation of a first frame, READ 1represents a reading out operation of the first frame, RESET 2represents a resetting operation of a second frame, and READ 2represents a reading out operation of the second frame.

It is assumed that in the first frame, after the OB region 7-1 c isscanned, a reading out operation is started from a V_shift1st row of theeffective pixel region 7-1 a, and an accumulation time period is Ts1.Besides, it is assumed that in the second frame, a reading out operationis started from a V_shift2nd row of the effective pixel region 7-1 a,and an accumulation time period is Ts2 which is longer than theaccumulation time period Ts1. A time period required for scanning onepixel row, namely, a time period required for one horizontal scanningperiod is assumed as Th.

A resetting operation for the first frame is started at a time t31. Atthe same time, a resetting operation is started also in the OB region7-1 c. When the counter 7-7 a starts a counting operation from a timet33, the counter 7-7 b also starts a counting operation at the sametime. In this case, the decoder 7-6 b may be driven in correspondencewith values continuous from the counter 7-7 a. Before the counter 7-7 afinishes the counting operation, namely, while the resetting operationof the counter 7-7 a for the OB region 7-1 c is being carried out, thedecoder 7-6 b starts a decoding operation from a preceding row withrespect to a pixel row where the resetting operation should be performedby a row number for carrying out the resetting operation of the OBregion 7-1 d. When the counting operation of the counter 7-7 a isfinished, the counter 7-7 a starts a resetting operation for a pixel rowwhere the resetting operation should be started, namely for the V_shift1 row.

The V_shift1 row is equivalent to a reading start position of theeffective pixel region 7-1 a for the first frame. In this case, thecounter 7-7 a continuously outputs a value which is larger than amaximum number of the decoder 7-6 a until the counter 7-7 a starts anext resetting operation. When the counter 7-7 b performs a countingoperation up to a time t35, the counter 7-7 c corresponding to thedecoder 7-6 c which scans a pixel row of the second pixel region startsa counting operation thereof in conjunction with the counting operationby the counter 7-7 b. In this case, the time t35 may be expressed asfollows:t35=t33+{(effective pixel number/2)−V_shift1}×Th  (12)

After the counter 7-7 c has started a counting operation, the counter7-7 c continuously performs the counting operation until the designatedlast pixel row of the effective pixel region is selected. After thecounting operations for all of the pixel rows have been finished, thecounter 7-7 c continuously outputs a count value which is larger thanthe maximum number of the decoder 7-6 c until a start signal produced inconjunction with the counter 7-7 b is subsequently supplied.

At a time t35, the resetting operation for (effective pixel rownumber/2)+(total row number of OB region)−V_shift1) rows is finished.Then, the counter 7-7 b performs such a resetting operation as to(V_shift1)−1−(total row number of OB region) rows which have not beenselected until the time t35. As a result, the counter 7-7 b resets thecount value, and executes a counting operation up to the(V_shift1)−1−(total row number of OB region) rows. After the counter 7-7b has performed the counting operation up to the (V_shift1)−1−(total rownumber of OB region) rows, this counter 7-7 b continuously outputs acount value which is larger than the maximum number of the decoder 7-6 bin a similar manner to the counters 7-7 a and 7-7 c until a next countstarting signal is supplied. As a result, all of the pixel rows can bereset at least one time within 1 frame.

In this example, if a count value of the counter 7-7 d has reachedV_shift+(reading row number), the counter 7-7 d continuously outputssuch a value larger than the maximum number of the decoder 7-5 until anext V synchronizing signal is supplied in a similar manner to othercounters. Both V_shift and a reading row number may be set to bearbitrary values, and hence the reading position can be controlled in asingle pixel unit.

In the second embodiment, imaging conditions such as an accumulationtime period, a reading start row, and a reading end row are set wheninstruction signals issued from a microcomputer (not illustrated) aresupplied to the timing generating circuit TG7-8. In this case, asequential operation when the microcomputer determines the imagingconditions will be describe as follows:

Condition 1: A time t36 precedes a time t37:t36<t37  (13)t36=t33+(Tf−Ts2)  (14)t37=t33+(effective pixel number/2)×Th−Ts1  (15)Condition 2: A time t39 precedes a time t40:t39<t40  (16)t39=t37+{(effective pixel number/2)+vertical OB rownumber−V_shift2}×Th  (17)t40=t22+(effective pixel number+vertical OB rownumber−V_shift1)×Th−Ts1  (18)Condition 3:V_shift×Th<Th−Ts2  (19)

If the formula (19) is modified, the following formula is established.Ts2<Tf−V_shift×Th  (20)

The condition 1 corresponds to such a condition for avoiding that in thedecoder 7-6 b, two pixel rows are simultaneously selected at the sametime. The condition 2 corresponds to such a condition for avoiding thatin the decoder 7-6 c, two pixel rows are simultaneously selected at thesame time. The condition 3 implies a condition in which the timing ofthe resetting operation for the second frame does not precede the timingof the reading out operation for the first frame in a temporal manner.

Moreover, when the condition 1 is modified, it becomes:Ts2−Ts1<Tf−(effective pixel row number/2)×Th  (21)

The second condition 2 becomes:Ts2−Ts1<{ΔV_shift−(effective pixel row number/2)}×Th+Tf  (22)

Assuming that Ts2 is an accumulation time period of a certain frame,symbol ΔTs2 is a change amount of the accumulation time period from theaccumulation time period Ts1 immediately preceding frame thereof. Also,symbol ΔV_shift corresponds toΔV_shift=V_shift2−V_shift1  (23).Assuming that a reading start position in a certain frame is V_shift2,ΔV_shift becomes a difference between V_shift2 and V_shift1 whichcorresponds to a reading start position immediately preceding framethereof.

FIG. 10 indicates a relationship between Ts2−Ts1 and Ts1 in a case wherethe maximum and minimum ΔV_shift are set to fixed values.

Until Ts1 becomes (effective pixel row number/2)×Th, the maximumchangeable Ts2−Ts1 becomes such a constant as Tf+{ΔV_shift−1−(effectivepixel row number/2)}×Th. This is determined by the condition 2. Then,the maximum changeable ΔTs2 is decreased at an inclination of −1. Insuch a case where an imaging operation is carried out in a constantframe rate, if the time period Ts1 becomesTs1=Tf+(ΔV_shift−1)×Th  (24),an accumulation time period cannot be prolonged. In order to prolong theaccumulation time period further, the frame rate is lowered and Tf isprolonged.

Both the accumulation time and the reading start position can bearbitrarily set within such a range capable of satisfying theabove-mentioned three conditions. As a result, the sensor can be drivenin response to a change in brightness when a moving picture is captured.Moreover, the sensor can be driven with respect to electronic vibrationisolation. Further, because the scanning circuits are formed not byshift registers, but by the decoders, the vertical scanning circuits canbe easily driven in various modes such as an addition mode, an interlacemode, a progressive mode, and a thinning-out mode.

In a case where ΔV_shift is a positive value, namely, a reading outregion is moved to a lower direction of a screen, as compared with thatof a preceding frame, in a row preceding the reading out region forΔV_shift, an accumulation time period becomes longer than that of thepixel of the reading out region. When light having high intensity hasbeen entered, there is such a risk that electric charges may be leakedfrom the pixel whose accumulation time period is long into the pixel ofthe reading out region. However, as described in the third embodiment,in a case where the scanning operation of the reset decoder has startedprior to such a total row number where the OB region should beactivated, the accumulation time period for the total row number of theOB region which is located adjacent to the effective pixel region can bemade equal to the accumulation time period for the reading out region.As a result, it is possible to suppress that the electric charges areleaked from the pixels which have been reset prior to the total rownumber of the OB region into the pixel of the effective pixel region. Inaddition, excessive charges generated in pixels located outside theabove-mentioned pixels are leaked into the previously reset pixels, andhence an adverse influence on the reading pixel region can besuppressed.

In the third embodiment, one reset decoder is set with respect to the OBregion, and two reset decoders are set with respect to the effectivepixel region, namely, three reset decoders are set in total.Alternatively, a dividing number, and a total row number allocated toone decoder may be arbitrary selected. Further, in a case where adividing number of the decoders and vertical scanning patterns arechanged, restrictions of driving conditions given under the dividingnumber and the vertical scanning pattern may be newly set.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2007-294438, filed Nov. 13, 2007, which is hereby incorporated byreference herein in its entirety.

1. A solid-state imaging apparatus comprising: a pixel region includinga plurality of pixels arranged in a matrix, each pixel including aphotoelectric conversion element, and a reset switch configured todischarge an electric charge of the photoelectric conversion element;and a first scanning circuit configured to supply a reset control signalfor controlling an operation of the reset switches, wherein the pixelregion and the first scanning circuit are disposed on a semiconductorsubstrate, the pixel region includes a first pixel region and a secondpixel region, the second pixel region includes pixel rows different frompixel rows included in the first pixel region, and the first scanningcircuit includes a first decoder configured to control an operation ofthe reset switch of each of the pixel rows arranged in the first pixelregion, and a second decoder configured to control an operation of thereset switch of each of the pixel rows arranged in the second pixelregion, wherein after the first decoder turns on successively the resetswitches of the plurality of the pixel rows included in the first pixelregion, the second decoder turns on successively the reset switches ofthe plurality of the pixel rows included in the second pixel region, andwhile the second decoder turns on successively the reset switches of theplurality of the pixel rows included in the second pixel region, thefirst decoder turns on successively the reset switches of the pluralityof the pixel rows included in the first pixel region.
 2. The solid-stateimaging apparatus according to claim 1, further comprising: in the pixelregion, an amplifying portion configured to amplify a signal based on acharge in the photoelectric conversion element, and a transfer switchconfigured to transfer the charge from the photoelectric conversionelement to the amplifying portion.
 3. The solid-state imaging apparatusaccording to claim 2, further comprising: a second scanning circuitconfigured to supply a transfer control signal for controlling anoperation of the transfer switch, wherein the second scanning circuitincludes a third decoder configured to generate the transfer controlsignal, and a logic circuit configured to generate the reset controlsignal and the transfer control signal to be supplied to a predeterminedpixel row.
 4. The solid-state imaging apparatus according to claim 3,further comprising: an optical black region arranged adjacent to thepixel region, and a fourth decoder configured to control an operation ofthe reset of the optical black region, wherein the logic circuitsupplies the transfer control signal to one part of the pixel rows inthe pixel region without supplying the transfer control signal toanother part of the pixel rows in the pixel region, and during a periodof controlling the reset operation by the fourth decoder, the firstdecoder controls the operation of the reset switch of a pixel row, whichis adjacent to the one part of the pixel rows in the pixel region andincluded in the another part of the pixel rows in the pixel region. 5.The solid-state imaging apparatus according to claim 1, furthercomprising an optical black region arranged adjacent to the pixelregion, and a fourth decoder configured to control a reset operation ofthe optical black region.
 6. The solid-state imaging apparatus accordingto claim 1, further comprising a plurality of counters, with eachcounter corresponding to one of the first and second decoders, and acontrol circuit configured to control each of the counters, wherein thecontrol circuit sets, at a predetermined value, an initial value of acount value to be supplied by each of the counters according to eachimage frame, and each of the decoders is controlled by each of the countvalues.
 7. The solid-state imaging apparatus according to claim 6,wherein the control circuit sets a reading out region and a non-readingout region in the first pixel region, and after the first decodercompletes turning on successively the reset switches of the plurality ofthe pixel rows included in the reading out region, the first decoderturns on the reset switch of the pixel row included in the non-readingout region.
 8. The solid-state imaging apparatus according to claim 6,wherein the counters supply the count values to the first and seconddecoders such that, at least once, all of the pixel rows are selectedframe by a frame.
 9. The solid-state imaging apparatus according toclaim 6, wherein after the initial value is set, the countercorresponding to the first decoder holds a maximum count value, and thecounter corresponding to the second decoder starts a count up of thecount value.